The invention described herein relates generally to electrical interconnections in semiconductor devices. In particular, the invention relates to an improved electrical interconnection for large bond pads, bus lines, and other large or wide electrical connections. The invention also addresses methods for forming such interconnections.
For electrical interconnections in semiconductor devices, large conducting surfaces are commonly connected to other conducting surfaces using many small interconnects that pass through many dot vias to electrically establish electrical connections. Such interconnections are commonly used for bond pads, bus lines, wide metal interconnects, as well as a host of other large electrical interconnect structures used in semiconductor electronic circuitry.
FIG. 1 is a schematic top down representation of one such structure as conventionally known in the art. A copper bond pad 101 is formed on a semiconductor substrate and electrically connected to a current line 102. In this example, the bond pad 101 is connected to a complementary bond pad (not shown in this view) formed on an overlying dielectric layer. The bond pad 101 has a number of slots 103 formed therein. The slots 103 are stress relief grooves formed in the bond pads 101. These stress relief grooves segment the larger metal masses into smaller areas, thereby avoiding metal xe2x80x9ccreepxe2x80x9d and other stress related issues. Commonly, these slots 103 pass completely through the bond pads 101 such that the underlying substrate is exposed. A dielectric layer is then formed over the bond pads 101. Later, the complementary bond pads are formed in the dielectric layer. In order to electrically connect the copper bond pad 101 with the overlying complementary bond pad, a multiplicity of dot vias 104 are formed in the dielectric layer. These dot vias 104 (called dot vias because of their substantially circular shape) are filled with copper material to provide a conduction path between the bond pad 101 and the overlying complementary bond pad. The multiplicity of dot vias 104 is often referred to as a sea of vias.
The cross-section A-Axe2x80x2 is depicted in FIG. 2 which illustrates the conduction paths between the bond pad 101 and the overlying complementary bond pad 111. The slots 103 in the bond pad 101, which are now filled with deposited dielectric material, are clearly depicted. Side views of sample dot vias 104 are well illustrated in this view.
Although suitable for their intended purpose, such conventional electrical interconnection approaches have certain limitations and drawbacks. One drawback is the large required size of the bond pads 101 (and 111). Another, somewhat related problem is the high electrical failure rate of the dot vias 104.
FIG. 3(a) is a close-up view of the bottom portion of a single representative dot via 104 as it makes an electrical connection with the underlying bond pad 101. The dot via 104 is lined with a diffusion barrier 112 and electrically contacts the underlying bond pad 101 through its bottom surface 113. The dot via 104 is encapsulated by the surrounding dielectric material 114. Because copper has a high diffusivity through the dielectric and silicon materials (e.g., dielectric layer 114), it is supplied with the barrier layer 112. This prevents the copper from diffusing into the surrounding dielectric materials and affecting dielectric leakage and potentially causing a host of copper contamination issues.
With continued use over time, such vias 104 are known to suffer from certain electromigration problems. FIG. 3(b) illustrates one manifestation of a typical electromigration problem. The electrical connection from bottom 104b of the dot via 104 to the underlying bond pad 101 is broken by the formation of a void 120 in the underlying copper bond pad 101. This relatively common occurrence is precipitated by the electromigration of copper in the bond pad 101 away from the material of the barrier layer 112. The depicted problem is especially troublesome because it causes a complete electrical disconnection between the dot via 104 and the underlying bond pad 101. Such electrical failures are so prevalent that they are factored in to the final size of the bond pad 101 and the number of dot vias 104. For example, the desired amount of current that must pass through the bond pad is determined. The number and size of dot vias necessary to carry the current are calculated, based upon the known dot via failure rates versus current density of vias. The predicted number of dot via failures are then factored in to obtain a final number of vias. This final number of vias is then used to determine the size of the bond pad. Therefore, in such conventional approaches, the bond pads are always larger than the minimum possible size. The bond pads are made even larger due to the need for the stress relief slots formed in the bond pads. Thus, in existing technologies, excessive surface area is taken up by the overly large electrical connectors (e.g., bond pads).
FIG. 3(c) depicts another type electromigration problem present in conventional interconnection structures. The electrical connection from bottom 104b of the dot via 104 to the underlying bond pad 101 is broken by the formation of a void 121 in the bottom portion of the dot via 104. This is precipitated by the electromigration of copper in the dot via 104 away from the material of the barrier layer 112. The depicted problem causes a substantial electrical disconnection between the dot via 104 and the underlying bond pad 101, thereby choking the amount of current that can pass through the via 104 down to a minimum. As with the above-described electromigration problem, larger than necessary bond pads are used to address the problem.
For the reasons described hereinabove, as well as other reasons, an improved inter-layer interconnection structure for large electrical connections and methods for its construction is needed.
In accordance with the principles of the present invention, an apparatus and method for fabricating a large electrical interconnection structure for use in semiconductor devices is disclosed.
Embodiments of the invention include an electrical interconnection structure for connection to large electrical contacts. This electrical interconnection includes a semiconductor substrate having a conductive interconnect pad formed thereon. A dielectric layer having a plurality of elongate openings is formed over the conductive interconnect pad. The elongate openings of the dielectric layer extend through the dielectric layer to the underlying pad. Elongate conductive contacts are formed in the elongate openings to establish electrical connections to the underlying pad.
In another embodiment, the electrical interconnection structure includes a semiconductor substrate having a copper pad layer formed with a plurality of elongate slots formed therein. The slots extend into the pad layer and have a long axis, a short axis, and sidewalls. A dielectric layer having a plurality of elongate bar trenches overlies the copper pad. The bar trenches extend through the dielectric layer. Elongate conductive contacts are formed in the plurality of elongate openings to establish electrical connections to the underlying copper pad layer. In some embodiments, the elongate conductive contacts are configured to electrically connect to the sidewalls of the copper pads. In the foregoing, and other embodiments, the long axes of the plurality of elongate bar trenches can be arranged substantially parallel to the long axes of the plurality of the slots formed in the copper pad. Alternatively, the long axes of the plurality of elongate bar trenches can be arranged transversely to the long axes of the plurality of the slots formed in the copper pad.
Other embodiments address the methods of manufacturing the electrical interconnection structures of the present invention.